FIG. 1 shows a first example of a conventional diagram of a voltage step-up device of the type to which embodiments of the present invention apply.
Such a converter is essentially formed of an inductance L in series with a rectifying diode D between two terminals E and S respectively defining a positive input terminal of a D.C. supply voltage Vdc and a negative output terminal of a D.C. voltage Vout of a higher level than voltage Vdc. Voltages Vdc and Vout are, in this example, referenced to a common ground M. For galvanic isolation, the input and output grounds may however be different. To perform the voltage step-up function, a switch K (generally, an N-channel MOS power transistor) connects junction point 1 of inductance L and diode D to ground M. Switch K is controlled by a pulse train provided by an electronic control circuit 2 (CTRL). During periods when switch K is on, power is built up in inductance L. During periods when switch K is off, this power is given back via diode D at the converter output. Most often, a power storage capacitor C connects terminals S and M to supply a load 3 (Q) connected between terminals S and M with a steady voltage. Capacitor C is sometimes omitted, either because a capacitor is included in load 3, or because it does not need a steady power supply.
The pulse train for controlling switch K may be a pulse train of fixed frequency and pulse-width modulated (PWM), a pulse train of fixed duty cycle but pulse-frequency modulated (PFM), or any other settable pulse train. Generally, circuit 2 receives an information REG relative to output voltage Vout to enable controlling on periods of switch K to maintain the desired voltage Vout.
A recurring problem of a step-up converter of the type shown in FIG. 1 is that in case of a short-circuit in load 3, the current stored in the inductance is no longer controllable, which results in a deterioration thereof.
A first known solution to overcome this phenomenon is shown in FIG. 1 and consists of providing a power cut-off circuit formed of a resistor in series with a switch Kd to short-circuit the starting inductance and in case of a detection of a short-circuit in the load. Such a power cut-off circuit can also directly short-circuit the series association of the diode and of the inductance.
At the converter starting or more generally when voltage Vout is smaller than voltage Vdc—which is measured by control circuit 2—switch Kd is permanently turned on and switch K remains off. This enables charging output capacitor C so that voltage Vout starts increasing. If control circuit 2 detects no increase in voltage Vout, it can then set to an alarm state after some time since this means a short-circuit on the load side.
A disadvantage of this solution is that the resistor causes a strong dissipation in the circuit and sets integration and bulk problems.
FIG. 2 shows a second conventional example of the control of a step-up converter enabling protection of the starting inductance of the circuit. In the example of FIG. 2, switch K has been shown in the form of an N-channel MOS transistor and load Q has not been shown.
According to the example, a P-channel MOS transistor 4 is interposed between the cathode of diode D and terminal S (positive electrode of capacitor C and/or of the load). The gate of transistor 4 is connected by a switch S1 either directly to source 6 of transistor 4, or to a potential smaller than this source, imposed by a Zener diode DZ. In practice, the diode anode is biased by a current source 5 connected, for example, to ground. As for switch K its gate is connected to point 1 by a Zener diode DZ2 in series with a switch S2 and to ground M by a Zener diode DZ3. The function of Zener diode DZ3 is to protect switch K by limiting its gate voltage. The function of diode DZ2 is to impose a potential difference between point 1 and the gate of transistor K when switch S2 is on. Finally, a switch S3 in series with a diode D3 is interposed between the output of circuit 2 providing the pulse train and the gate of transistor K.
In normal operation, switch S3 is on, switch S2 is off, and switch S1 is in the position where it connects the gate of transistor 4 to the potential set by diode DZ, which turns on this transistor. Switch K is thus normally controlled by means of a pulse train, which causes successive phases of charge and discharge of inductance L in capacitor C.
In the case of a short-circuit in the load (between terminals S and M), said short-circuit must be detected by annex means (for example by monitoring by means of signal REG entering control circuit 2′ that voltage Vout is at approximately ground). Once the short-circuit has been detected, circuit 2′ controls the turning-off of switch S3 and the turning-on of switch S2 to put into service the active clamping stage of the gate voltage of NMOS transistor K formed by diode DZ2. In practice, a resistor R3 grounding the gate of transistor K is provided to enable discharge thereof. Once the gate of transistor K has been protected, circuit 2′ causes the switching of switch S1 to short-circuit its gate and source to turn it off. The turning-off of transistor 4 isolates inductance L from the rest of the circuit, and thus from the short-circuit. In the absence of diode DZ2, this turning-off would cause an overvoltage between the gate and the source of transistor K. This overvoltage is here avoided by means of diode DZ2 which clamps the voltage between the gate and the drain of transistor K.
A disadvantage of the protection circuit of FIG. 2 is that it requires a specific switch control sequence. In particular, the turning-off of transistor 4 must only occur once transistor K has been blocked by the turning-off of switch S3 and the clamping stage has been put into service by the turning-on of switch S2.
Another disadvantage of the circuit of FIG. 2 is that the amount of power stored in inductance L is not controlled.
Another disadvantage is that such a circuit is relatively bulky due to the number of annex switches that it requires.
Another disadvantage is that the restarting of the circuit generally requires a timing delay from the detection of a problem. In some cases, the diode D is replaced by a transistor controlled by the circuit 2 (FIG. 1) or 2′ (FIG. 2) so as to provide a synchronous rectification and avoid a voltage drop across diode D.